With the advancement of remote sensing technology, there is an increasing demand for high-resolution remote sensing images. However, due to the limitations of optical devices, insufficient sensor resolution, and factors such as satellite orbital height, the imaging equipment captured remote sensing images often cannot achieve the ideal resolution, and the imaging effect is not satisfactory, which brings great trouble to researchers in extracting and analyzing the features of remote sensing images. To solve this problem, a modular and reconfigurable system architecture is used, and a multi-row buffer pipeline mechanism is implemented based on the FPGA hardware platform to design real-time processing modules such as bilateral filtering, upsampling, and downsampling. Image pyramids and Laplacian pyramids are constructed, and image interpolation is performed layer by layer to achieve high-resolution imaging. The overall system hardware design is based on the Xilinx XC7A35T FPGA chip and its synthesis results are analyzed for performance indicators. The system has good portability. With the clock frequency of the image processing modules in the system set to 180 MHz, the delay is less than 5 ms, which can meet the real-time requirements of the system.