A large number of digital devices are used for the digital phased array device, such as high-speed AD and FPGA. When the device is powered on or restarted each time, there is randomness for the initial phase of the digital device frequency reference clock, which results in time delay jitter and causes changes of ranging zero values of the device. In engineering applications, a system zero value calibration is usually performed when the device is powered on or restarted each time, it can ensure the accuracy of the ranging zero value. However, this processing undoubtedly increases the complexity of the system work mode. This paper proposes a method to achieve fixed transmission delay by adding preamble pulse control. After adopting this method, it is not necessary to repeat zero value calibration every time the power is turned on, which simplifies the use mode of equipment. The simulation test results and engineering practice have verified the effectiveness of this method.